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| september 2013 doc id 022048 rev 2 1/51 1 l9659 octal squib driver asic for safety application features 8 deployment drivers with spi selectable firing current and times capability to deploy the squib with 1.2 a (min)/2 ms, 1.75 a (min)/1.0 ms and 1.75 a (min)/0.65 ms between vres of 7 v to 37 v capability to deploy the squib with 1.5 a (min)/2 ms between vres of 7 v to 25 v firing capability to d eploy all channels simultaneously independently controlled high-side and low- side mos for diagnosis analog output available for resistance measurement squib short to ground, short to battery and mos diagnostic available on spi register capability to deploy the squib the low side mos is shorted to ground 4 fire enable inputs 5.5 mhz spi interface low voltage internal reset 2 kv esd capability on all pins package: lqfp64 technology: st proprietary bcd5 (0.65 m) rohs compliant description the l9659 is intended to deploy up to 8 squibs. squib drivers are sized to deploy 1.2 a minimum for 2 ms, 1.75 a minimum for 1 ms and 1.75 a minimum for 0.65 ms during load dump along with 1.5 a minimum for 2 ms for vres voltages less than 25 v. full diagnostic capabilities of the squib interface are provided. lqfp64 (10x10x1.4mm) ' ! 0 ' 0 3 table 1. device summary order code amb. temp range, ? cpackage packing l9659 -40 to +95 lqfp64 tray L9659TR -40 to +95 lqfp64 tape and reel www.st.com
contents l9659 2/51 doc id 022048 rev 2 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 absolute maximum degraded operating ratings . . . . . . . . . . . . . . . . . . . . 10 2.3 operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.2 electrical characteristics - squib deployment drivers and diagnostics . . 12 2.4.3 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 general functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 power on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.2 resetb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.3 reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.4 loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.5 vresx capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.6 supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.7 ground connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.1 spi pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 squib drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.1 firing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.2 firing current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.3 fire enable (fen) function description . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.4 squib diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.5 spi register definition for squib functions . . . . . . . . . . . . . . . . . . . . . . . . 31 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 l9659 list of tables doc id 022048 rev 2 3/51 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. absolute maximum degraded operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. general - dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. squib deployment drivers and diagnostics - dc el ectrical characteristics . . . . . . . . . . . . . 12 table 8. spi timing - dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. features that are accessed/controlled for the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. spi mosi/miso response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. how faults shall be interpreted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. diagnostic mode hss selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. diagnostic mode 3 vresx selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. miso responses to various events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. command description summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 table 16. configuration mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17. configuration mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 18. deployment mode 1 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. deployment mode 2 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 20. diagnostic selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 21. diagnostic mode ls fet selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 22. diagnostic mode hs fet selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 table 23. diagnostic mode hss selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 24. diagnostic mode vresx selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 table 25. channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 26. mosi diagnostic mode 1 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 27. deploy_statusx flag and the deploy_successx flag conditions. . . . . . . . . . . . . . 44 table 28. mosi monitor mode 2 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 29. current measurement channel selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 30. mosi monitor mode 3 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 31. mosi monitor mode 4 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 32. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 list of figures l9659 4/51 doc id 022048 rev 2 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. mos settling time and turn-on time 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. miso loading for disable time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. por timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. deployment drivers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. driver activation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. squib diagnostics block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. lqfp64 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 l9659 block diagram and pin description doc id 022048 rev 2 5/51 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description ' ! 0 ' 0 3 $ e p l o y m e n t $ r i v e r $ i a g n o s t i c s 4 % 3 4 2 % 3 % 4 6 $ $ 3 1 ( 3 1 , 3 1 ( 3 1 , 3 1 ( 3 1 , 3 1 ( 3 1 , 6 2 % 3 ' . $ 6 2 % 3 ' . $ 6 2 % 3 ' . $ 6 2 % 3 ' . $ ! / 5 4 # 3 ? $ 3 # , + - / 3 ) - ) 3 / & % . & % . & % . & % . ' . $ ! ' . $ 3 0 ) 3 q u i b $ e p l o y m e n t $ i a g n o s t i c s 0 i n 3 1 ( 3 1 , 3 1 ( 3 1 , 3 1 ( 3 1 , 3 1 ( 3 1 , 6 2 % 3 ' . $ 6 2 % 3 ' . $ 6 2 % 3 ' . $ 6 2 % 3 ' . $ ) 2 % & table 2. pin description pin # pin name description i/o type reset state 1 miso spi data out output hi-z 2 nc no connect - - 3 fen1 fire enable for channels 0 and 1 input pulldown 4 fen2 fire enable for channels 2 and 3 input pulldown 5 resetb reset pin input pullup 6 gnd ground (analog & digital) - - 7 vdd vdd supply voltage input - block diagram and pin description l9659 6/51 doc id 022048 rev 2 8 fen3 fire enable for channels 4 and 5 input pulldown 9 fen4 fire enable for channels 6 and 7 input pulldown 10 nc no connect - - 11 nc no connect - - 12 cs_d spi chip select for deployment driver input pullup 13 mosi spi data in input hi-z 14 nc no connect - - 15 nc no connect - - 16 sclk spi clock input hi-z 17 gnd4 power ground for loop channel 4 - - 18 sql4 low side driver output for channel 4 output pulldown 19 sqh4 high side driver output for channel 4 output hi-z 20 vres4 reserve voltage for loop channel 4 input - 21 vres5 reserve voltage for loop channel 5 input - 22 sqh5 high side driver output for channel 5 output hi-z 23 sql5 low side driver output for channel 5 output pulldown 24 gnd5 power ground for loop channel 5 - - 25 gnd6 power ground for loop channel 6 - - 26 sql6 low side driver output for channel 6 output pulldown 27 sqh6 high side driver output for channel 6 output hi-z 28 vres6 reserve voltage for loop channel 6 input - 29 vres7 reserve voltage for loop channel 7 input - 30 sqh7 high side driver output for channel 7 output hi-z 31 sql7 low side driver output for channel 7 output pulldown 32 gnd7 power ground for loop channel 7 - - 33 test test pin input pulldown 34 vsdiag supply for deployment driver diagnostics input - 35 nc no connect - - 36 reserved factory testmode output - - 37 reserved factory testmode output - - 38 nc no connect - - 39 nc no connect - - 40 nc no connect - - 41 nc no connect - - 42 nc no connect - - table 2. pin description (continued) pin # pin name description i/o type reset state l9659 block diagram and pin description doc id 022048 rev 2 7/51 43 nc no connect - - 44 nc no connect - - 45 nc no connect - - 46 iref external current reference resistor output - 47 agnd ground reference for aout - - 48 aout analog output for loop diagnostics output hi-z 49 gnd3 power ground for loop channel 3 - - 50 sql3 low side driver output for channel 3 output pulldown 51 sqh3 high side driver output for channel 3 output hi-z 52 vres3 reserve voltage for loop channel 3 input - 53 vres2 reserve voltage for loop channel 2 input - 54 sqh2 high side driver output for channel 2 output hi-z 55 sql2 low side driver output for channel 2 output pulldown 56 gnd2 power ground for loop channel 2 - - 57 gnd1 power ground for loop channel 1 - - 58 sql1 low side driver output for channel 1 output pulldown 59 sqh1 high side driver output for channel 1 output hi-z 60 vres1 reserve voltage for loop channel 1 input - 61 vres0 reserve voltage for loop channel 0 input - 62 sqh0 high side driver output for channel 0 output hi-z 63 sql0 low side driver output for channel 0 output pulldown 64 gnd0 power ground for loop channel 0 - - table 2. pin description (continued) pin # pin name description i/o type reset state block diagram and pin description l9659 8/51 doc id 022048 rev 2 1.3 application schematic figure 2. application schematic ' ! 0 ' 0 3 # v r e s ? 6 2 % 3 6 2 % 3 6 2 % 3 6 2 % 3 # 3 ? $ - / 3 ) 3 # , + - ) 3 / 3 0 ) 3 q u i b $ e p l o y m e n t $ i a g n o s t i c s ) 2 % & 2 ) 2 % & 3 1 ( 3 1 , # v r e s ? 6 2 % 3 6 2 % 3 6 2 % 3 6 2 % 3 ' . $ 3 1 ( 3 1 , ' . $ 3 1 ( 3 1 , ' . $ 3 1 ( 3 1 , ' . $ 3 1 ( 3 1 , ' . $ 3 1 ( 3 1 , ' . $ 3 1 ( 3 1 , ' . $ 3 1 ( 3 1 , ' . $ $ e p l o y m e n t $ r i v e r s $ i a g n o s t i c s & % . & % . & % . & % . 6 $ $ 4 % 3 4 ' . $ 6 3 $ ) ! ' ! / 5 4 ! ' . $ 2 % 3 % 4 + 7 4 o ! $ # ? & ? & ? & 0 i n 6 $ $ l9659 electrical specifications doc id 022048 rev 2 9/51 2 electrical specifications 2.1 absolute maximum ratings the following maximum ratings are continuous absolute ratings; exceeding any one of these values may cause permanent damage to the integrated circuit. table 3. absolute maximum ratings symbol parameter value unit v dd (1) supply voltage - 0.3 to 5.5 v v sdiag supply voltage for squib diagnostics - 0.3 to 40 v vresx vres voltage (vres0, vres1 , vres2, vres3, vres4, vres5, vres6, vres7) - 0.3 to 40 v sqhx squib high side drivers (sqh0, sqh1, sqh2, sqh3, sqh4, sqh5, sqh6, sqh7) - 0.6 to 40 v sqlx squib low side drivers (sql0, sql1, sql2, sql3, sql4, sql5, sql6, sql7) - 0.3 to 40 v test test pin -0.3 to 40 v v i discrete input voltage (resetb, cs_d, sclk, mosi, fen1, fen2, fen3, fen4, iref) - 0.3 to 5.5 v v o discrete output voltage (miso, aout) - 0.3 to 5.5 v agnd analog output reference -0.3 to 5.5 v gndx ground (gnd0, gnd1, gnd2, gnd3, gnd4, gnd5, gnd6, gnd7) -0.3 to 5.5 v t j (2) maximum steady-state junction temperature 150 c t amb ambient temperature -40 to 95 c t stg storage temperature -65 to 150 c r th j amb thermal resistance junction to ambient (on fr-4 board) 46 c/w the following maximum ratings are up to 48 hours; exceeding any one of these values for longer than a total time of 48 hours may cause permanent damage to the integrated circuit. v dd supply voltage - 0.3 to 6.0 v v i discrete input voltage (resetb, cs_d, sclk, mosi, fen1, fen2, fen3, fen4, iref) - 0.3 to 6.0 v v o discrete output voltage (miso, aout) - 0.3 to 6.0 v agnd analog output reference -0.3 to 6.0 v gndx ground (gnd0, gnd1, gnd2, gnd3, gnd4, gnd5, gnd6, gnd7) -0.3 to 6.0 v t j (2) maximum steady-state junction temperature 150 c t amb ambient temperature -40 to 95 c t stg storage temperature -65 to 150 c r th j amb thermal resistance junction to ambient (on fr-4 board) 46 c/w 1. exceeding a v dd of 5.1v during a deployment may cause damage 2. to allow for deployment the maximum steady state junction temperature cannot exceed 130c. under the operating ratings defined in section 2.3 the steady state j unction temperature will not exceed 130c. electrical specifications l9659 10/51 doc id 022048 rev 2 2.2 absolute maximum degraded operating ratings under the following deviations to the ratings indicated in section 2.3 the l9659 performance will be degraded and not meet the electr ical characteristics outlined in section 2.4 . at minimum the spi and diagnostics will function bu t not meet spec ified electrical parameters. note: the above is provided for informational pur poses only and will result in degraded operation. under the above conditions the spi will be func tional as well as di agnostics, though the electrical performance may not conform to the parameters outlined in section 2.4 . firing requirements as indicated in section 2.4 may not be met with the conditions above. 2.3 operating ratings comments: vsdiag supply will provide power for squib resistance and hss diagnostics vdd will be used for all internal functions as we ll as short to battery/ground and high squib resistance diagnostics. table 4. absolute maximum degraded operating ratings symbol parameter value unit v dd supply voltage 4.5 to 5.5 v v sdiag supply voltage for squib diagnostics 7 to 40 v v res vres voltage (vres0, vres1 , vres2, vres3, vres4, vres5, vres6, vres7) 7 to 40 v v i discrete input voltage (resetb, depen, cs_d, sclk, mosi, fen1, fen2, fen3, fen4, iref) - 0.3 to (vdd +0.3) v v o discrete output voltage (miso, ao ut) -0.3 to (vdd + 0.3) v t j junction temperature -40 to 150 c table 5. operating ratings symbol parameter value unit v dd supply voltage 4.9 to 5.1 v v sdiag supply voltage for squib diagnostics 7 to 37 v v resx vres voltage (vres0, vres1, vres2, vres3, vres4, vres5, vres6, vres7) 7 to 37 v v i discrete input voltage (r esetb, cs_d, sclk, mosi, fen1, fen2, fen3, fen4, iref) - 0.3 to (v dd +0.3) v v o discrete output voltage (miso, aout) -0.3 to (vdd + 0.3) v t amb ambient temperature -40 to 95 c r th j-amb thermal resistance junction to ambient (on fr-4 board) 46 c/w l9659 electrical specifications doc id 022048 rev 2 11/51 2.4 electrical characteristics 2.4.1 general 4.9 v ? v dd ? 5.1 v; 7 v ? v resx ? 37 v; 7 v ? v sdiag ? 37 v; fen1 = fen2 = fen3 = fen4 = v dd ; r_ref = 10 k ? , 1 %, 100 ppm; -40 c ? t a ? +95 c; unless other specified. table 6. general - dc electrical characteristics symbol parameter test condition min. typ. max. unit osc internal oscillator frequency tested with 10k , 1%, 100ppm iref resistor 4.75 - 5.25 mhz v rst1 internal voltage reset vdd after de-glitch time (tpor) see figure 7 vdd level for l9659 to report reset condition -deployment drivers are disabled 4.0 - 4.5 v v rst2 internal voltage reset vdd with no de-glitch time see guaranteed by design 2.1 - 3.0 t por por de-glitch timer timer for vrst1 5 - 25 s i dd input current vdd no squib diagnostics. no deployment. - - 15 ma resistance measurement diagnostics with no fault condition present. --17 short to ?0.3v on sql; vrcm active - - 35 during deployment - - 15 r iref_h resistance threshold iref - - - 60.0 k ? r iref_l -2.0--k ? v ih_resetb input voltage threshold resetb ---2.0v v il_resetb -0.8--v v hys_rst - 100 - 300 mv v ih_test input voltage threshold test guaranteed by design - 3.2 - v i testpd input pull-down current test 1.0 - 2.5 ma i aout_shrt aout pin current limit aout short to ground during squib resistance diagnostics --20ma i resetpu input pull-up current resetb resetb = vih to gnd -10 - -50 a i resx quiescent current for vresx during hss test current per pin during hss test excluding selected channel - - 10 a v ih input voltage threshold (mosi, sclk, cs_d) input logic = 1 - - 2.0 v v il input logic = 0 0.8 - - v v hyst input hysteresis (mosi, sclk, cs_d) 100 - 300 mv i lkgd input leakage current mosi, sclk vin = vdd - - 1 a vin = 0 to vih -1 - - a electrical specifications l9659 12/51 doc id 022048 rev 2 2.4.2 electrical characte ristics - squib deployment drivers and diagnostics 4.9 v ? v dd ? 5. 1v; 7 v ? v resx ? 37 v; 7 v ? v sdiag ? 37 v; fen1 = fen2 = fen3 = fen4 = v dd ; r_ref = 10 k ? , 1%, 100 ppm; -40 c ? t a ? +95 c; c_vres0_1 ? 68nf; c_vres2_3 ? 68nfc_vres4_5 ? 68nf; c_vres6_7 ? 68nf; unless other specified. i pu_cs input pull-up current cs_d vin = vih to gnd -10 - -50 a v oh output voltage miso ioh = -800a vdd? 0.8 --v v ol iol = 1.6ma - - 0.4 v i hi_z tri-state current miso miso = vdd - - 1 a miso = 0v -1 - - a table 6. general - dc electrical characteristics (continued) symbol parameter test condition min. typ. max. unit table 7. squib deployment drivers and dia gnostics - dc electrical characteristics symbol parameter test condition min. typ. max. unit general i lkgsqh leakage current sqh vsdiag = vdd = 0, vres = 37v, vsqh = 0v - - 50 a i lkgvres bias current vresx vsdiag = 18v; vdd = 5v; vres = 37v; sqh shorted to sql - - 10 a i lkgsql leakage current sql vsdiag = vdd = 0, vsql = 18v -10 - 10 a i pd pulldown current sql vsql = 1.5v to 20v 3.3 - 4.1 ma v bias diagnostics bias voltage nominal 3.6v -5% vdd* 0.72 +5% v short to battery/ground di agnostics - rsqb from 0 ? to open i svrcm maximum diagnostics bias current limit short to battery or ground test active vsqh = 0v 5-20ma r stb short to battery resistance threshold vbatt = 6.5v 1.92 - 3.42 k ? vbatt = 16v 8.61 - 13.98 k ? vbatt = 20v 11.42 - 18.42 k ? i stb short to battery current threshold -0.9-1.42ma r stg short to ground threshold - 1.07 - 2.1 k ? i stg short to ground current threshold - 1.8 - 3.2 ma l9659 electrical specifications doc id 022048 rev 2 13/51 t diagtimeout diagnostic delay time from/cs ? until test results are valid, output voltage change 0v to vdd * 0.72 c sqhx = 0.12f c sqlx = 0.12f --300s high side safing diagnostics i src_hss diagnostic current into selected vresx pin during test normal conditions 710 - 950 a i hss_8 current during diagnostic all 8 vresx pins tied together 710 - 1020 a r hssnorm_th normal resistance range when running high side safing diagnostics all 8 vresx pins tied together 1.4 - 2.5 k ? v hssnorm_r ange normal voltage range between vsdiag and vresx pin) when running high side safing diagnostics all 8 vresx pins tied together 1.0 - 2.5 v v hssshort_th short voltage threshold between vsdiag and vresx pin) all 8 vresx pins tied together 0.5 - 1.0 v v hssopen_th open voltage threshold between vsdiag and vresx pin) all 8 vresx pins tied together 2.5 - 4.0 v t diagtimeout diagnostic delay time from/cs ? until test results are valid, c sqhx = 0.12f c sqlx = 0.12f - - 500 s voltage measurement diagnostics (vresx) i resx max diagnostic current into v resx pin normal conditions - - 50 a v vresxlo_th low voltage threshold for vresx pin -5.0-7 v v vresxhi_th high voltage threshold for vresx pin - 13.7 - 18.0 v t diagtimeout diagnostic delay time from/cs ? until test results are valid. - - 100 s table 7. squib deployment drivers and diagnostics - dc electrical characteristics (continued) symbol parameter test condition min. typ. max. unit electrical specifications l9659 14/51 doc id 022048 rev 2 mos diagnostics i _mos mos test max current normal conditions - - i svrcm ma t shutoff ls/hs mos turn off under fault condition time is measured from the valid ls/ hs mos current > 100ma to the ls/hs turn off --4s t fettimeout fet timeout normal conditions - - 100 s high squib resist ance diagnostics r sqhiz high load resistance threshold -1.07-2.1k ? i hr high resistance current threshold -i stg ma t diagtimeout mos diagnostic delay time from/cs ? until test results are valid, c sqhx = 0.12f c sqlx = 0.12f --300s squib resistance diagnostics v oh output voltage aout high saturation voltage; i aout = -500a vdd- 0.2 --v v ol low saturation voltage; i aout = +500a --0.2v i z tri-state current aout aout = vdd - - 1 a aout = 0v -1 - a r sqb range load resistance range - 0 - 10.0 ? v aout resistance measurement analog output tolerance v aout = 0 ? ? r sqb < 3.5 ? v aout - 0.095v - v aout + 0.095v v 3.5 ? ? r sqb ? 10 ? v aout 0.95v - v aout 1.05v v i src resistance measurement current source v dd = 5.0v; v sdiag = 7.0v to 37v 38 - 42 ma i sink resistance measurement current sink ipd off, vsqlx = 4 v 45 - 57 ma i slew rmeas current di/dt 30% - 70% of isrc 2 - 11 ma/s v cmpr voltage threshold on squib pin to shutdown isrc - 2.65 - 3.25 v t isrcshtdwn shutdown time guaranteed by design - - 30 s vlsdrsqb lsd (v_sql) voltage during resistance measure - 0.8 - 2.2 v table 7. squib deployment drivers and diagnostics - dc electrical characteristics (continued) symbol parameter test condition min. typ. max. unit vdd 1 9.75 ----------- 0.08 r sqb ? --------------- ? ?? ?? + ? l9659 electrical specifications doc id 022048 rev 2 15/51 t r_wait rmeas wait time wait time before aout voltage is stable for adc reading r aout= 5.1k ? ; c aout =10nf - - 300 s fenx input pins t fenfilter minimum pulse width - 12 - 16 s i fenpd internal pull-down current vin = vil to vdd 20 - 50 a v fenlo input low voltage threshold - 0.8 - - v v fenhi input high voltage threshold - - - 2.0 v t fenlatch fen latch timer - 0 - 512 ms t flacc fen latch timer accuracy - - 20% - 20 % deployment drivers t resolution diagnostic timing / resolution i hs ? i meas , 0s ? t measure_time ? 3.7ms c squib _hi = 0.12f c squib _lo = 0.12f 22.5 25 27.5 s t accuracy diagnostic time acurracy --2lsb i meas high side driver current limit detect threshold guaranteed by design i hsx x 0.90 - i hsx x 0.99 a r dsontotal total high and low side mos on resistance high side mos + low side mos d9:d8=?11?; v res = 7v; i = 1.6a @95c --2.0 ? r dsonhs high side mos on resistance d9:d8=?11?; vres = 7v; tamb = 95c; ivres = 1.6a; -0.3 0.8 ? r dsonls low side mos on resistance - 0.6 1.2 ? i hs_12a high side deployment current limit configuration mode 1 bits d9:d8=?00? sqhx shorted to ground; v res = 7 to 37v 1.21 - 1.47 a i hs_15a configuration mode 1 bits d9:d8=?01? sqhx shorted to ground; v res = 7 to 25v 1.51 - 1.85 a i hs_175a configuration mode 1 bits d9:d8=?11? sqhx shorted to ground; v res = 7 to 37v 1.76 - 2.14 a t ilim low side mos shutdown under short to battery v sqblo =18v 90 - 110 s i ls low side mos current limit 2.2 - 4.0 a table 7. squib deployment drivers and diagnostics - dc electrical characteristics (continued) symbol parameter test condition min. typ. max. unit electrical specifications l9659 16/51 doc id 022048 rev 2 figure 3. mos settling time and turn-on time 2 t settle firing current settling time time from fire command cs_d rising edge to where firing current remains within specified limits c squib _hi = 0 to 0.12f c squib _lo = 0 to 0.12f - - 150 s t deploy-2ms deployment time vres = 7vto 37@ i hs_12a vres = 7vto 25@ i hs_15a for i hs_12a and i hs_15a firing current measured from cs_d rising edge 2.15 - 2.5 ms t deploy-1ms v res = 7vto 37v for i hs_175a firing current measured from cs_d rising edge 1.15 - 1.40 ms t deploy-0.65ms v res = 7vto 37v for i hs_175a firing current measured from cs_d rising edge 0.65 - 0.85 ms table 7. squib deployment drivers and diagnostics - dc electrical characteristics (continued) symbol parameter test condition min. typ. max. unit ) # 3 ? $ 2 i s i n g % d g e 0 % ! + t s e t t l e ) ( 3 ? x x ! - a x i m u m ) ( 3 ? x x ! - i n i m u m ' ! 0 ' 0 3 l9659 electrical specifications doc id 022048 rev 2 17/51 2.4.3 spi timing all spi timing is performed with a 150 pf load on miso unless otherwise noted 4.9v ? v dd ? 5.1v; 7v ? v resx ? 37v; 7v ? v sdiag ? 37v; fen1 = fen2 = fen3 = fen4 = v dd ; r_ref = 10k ? , 1%, 100ppm; -40c ? t a ? +95c; c_vres0_1 ? 68nf; c_vres2_3 ? 68nf; c_vres4_5 ? 68nf; c_vres6_7 ? 68nf; unless other specified. . table 8. spi timing - dc electrical characteristics no. symbol parameter min. typ. max. unit - fop transfer frequency dc - 5.50 mhz 1 t sck sclk period 181 - - ns 2 t lead enable lead time 65 - - ns 3 t lag enable lag time 50 - - ns 4 t sclkhs sclk, high time 65 - - ns 5 t sclkls sclk, low time 65 - - ns 6 t sus mosi, input setup time 20 - - ns 7 t hs mosi, input hold time 20 - - ns 8 t a miso, access time - - 60 ns 9 t dis (1) miso, disable time - - 100 ns 10 t vs miso, output valid time - - 60 ns 11 t ho (1) miso, output hold time 0 - - ns 12 t ro rise time (design information) - - 30 ns 13 t fo fall time (design information) - - 30 ns 14 t csn cs_d, negated time 640 - - ns 15 t clkn time between cs rising edge and first transition of sclk must be higher than tclkn. it happens when multiple devices are connected to the same sclk and mosi but with different chip select. 500 - - ns 1. parameters t dis and t ho shall be measured with no additional capacitiv e load beyond the normal te st fixture capacitance on the miso pin. additional capacitanc e during the disable time test erroneous ly extends the measured output disable time, and minimum capacitance on miso is the worst case for output hold time. electrical specifications l9659 18/51 doc id 022048 rev 2 figure 4. spi timing diagram figure 5. miso loading for disable time measurement ' ! 0 ' 0 3 3 # , + $ / . g 4 # ! 2 % - ) 3 / - / 3 ) # 3 ? $ t , ! ' t # 3 . f / 0 t 3 # , + ( 3 t , % ! $ t 3 # , + , 3 t 6 3 t ! t 3 5 3 t ( 3 t 2 / t & / t ( / t $ ) 3 - 3 " ) . , 3 " ) . $ ! 4 ! - 3 " / 5 4 , 3 " / 5 4 $ ! 4 ! t # , + . ' ! 0 ' 0 3 6 6 6 6 # 3 - ) 3 / 6 $ $ - ) 3 / t $ ) 3 k k l9659 functional description doc id 022048 rev 2 19/51 3 functional description 3.1 overview the l9659 is an integrated circuit to be used in air bag systems. its main functions include deployment of air bags. the l9659 supports 8 deployment loops. 3.2 general functions 3.2.1 power on reset (por) the asic has a power on reset (por) circui t, which monitors vdd voltage. when vdd voltage falls below v rst1 for longer than or equal to t por , all outputs are disabled and all internal registers are reset to their default condition. a second reset level, v rst2 , also monitors vdd but uses no filter time and will di sable all outputs and all internal registers are reset to their default condition when vdd falls below the reset threshold. figure 6. por timing 3.2.2 resetb the resetb pin is active low. the effects of resetb are similar to those of a por event, except during a deployment. when a deployment is in-progress, the l9659 will ignore the resetb signal. however, it will shut itself down as soon as it detects a por condition. when the deployment is completed and resetb signal is asserted, th e l9659 disables its outputs and reset its internal registers to their default states. a de-glitch timer is provided for the resetb pin. the time r protects this pin against spurious glitches. the l9659 n eglects resetb signal if it is asserted for shorter than tglitch. resetb has an internal pu ll-up in case of an open circuit. ' ! 0 ' 0 3 6 $ $ - ) . 6 2 3 4 6 2 3 4 ) . 4 % 2 . ! , 2 % 3 % 4 4 0 / 2 - i n 4 0 / 2 - i n a 4 a 4 0 / 2 - a x 4 0 / 2 - i n a 4 a 4 0 / 2 - a x functional description l9659 20/51 doc id 022048 rev 2 3.2.3 reference resistor iref pin shall be connected to vdd supply through a resistor, riref. when the l9659 detects the resistor on iref pin is larger than riref_h or smaller than riref_l, it goes into a reset condition. all outputs are disabled and all internal registers are reset to their default conditions. 3.2.4 loss of ground gnd when the gnd pin is disconnected from pc-board ground, the l9659 goes in reset condition. all outputs are disabled and all internal registers are reset to their default conditions. gnd0-gnd7 a loss of power-ground (gnd0 ? gnd7) pin/s disables the respective low side driver/s on sqlx. however, the high side driver of the re spective channel will still be able to be turned on. thus under the scenario where the low si de is shorted to ground the l9659 will be able to provide the programmed firing current for the specified time. an open gndx connection on any channel has no affect on the other channels. an open gndx condition will be detected us ing the low side mos diagnostics. agnd the agnd pin is a reference for aout pin. when agnd loses its connection, the voltage on aout pin is pulledup to vdd voltage and l9659 goes in reset condition. all outputs are disabled and all internal register are reset to their default conditions. 3.2.5 vresx capacitance to ensure all diagnostics function properly a ty pical capacitor of equal to or greater than 68nf is required close to the firing supply pi ns. thus minimum of 4 capacitors are required with one placed close to the vres0 and vres1 pins and a second capacitor will be close to the vres2 and vres3 pins and a third capacitor will be cl ose to the vres4 and vres5 pins and a forth capacitor will be cl ose to the vres6 and vres7 pins. 3.2.6 supply voltages the primary current sources for the different functions of the asic are as follows: vresx - firing currents along with hss and hs fet diagnostic currents vsdiag - squib resistance and hss diagnostics vdd will be used for all internal functions as well as short to battery/ground and high squib resistance diagnostics. 3.2.7 ground connections gnd pin (6) is not connected internally to other ground pins (agnd or power ground gndx). a ground plane is needed to directly connect the gnd pin. this ground plane needs to be isolated from the high current ground for the squib drivers to prevent voltage shifts. agnd pin should be connected to ground plane too to minimize drop versus ground reference of adc that capture aout voltage. l9659 functional description doc id 022048 rev 2 21/51 3.3 serial peripheral interface (spi) the l9659 contains one serial peripheral interf aces for control of the squib functions. the following table shows features that are accessed/controlled by the spi. . the software reset accessed over spi will reset squib functions. the l 9659 has a counter to verify the number of clocks in sclk. if the nu mber of clocks in sclk is not equal to 16 clocks while cs_d is asserted, it ignores the spi message and sends a spi fault response. l9659 computes spi error length flag through counting the number ofsclk rising edges occurring when cs_d is active. if the first sc lk rising edge occurs when cs_d is inactive and the falling edge occurs when cs_d is low, it is considered as valid edge. mosi commands contain several bits not used, all those bits must be 0. commands are not recognized valid if one or more not used bits are not 0. 3.3.1 spi pin descriptions chip select (cs_d) chip-select inputs select the l9659 for serial transfers. cs_d can be asserted at any given time and are active low. when chip-select is asserted, the respective miso pin is released from tri-state mode, and all status information is latched into the spi shift register. while chip-select is asserted, register data is shifted into mosi pin and shifted out of miso pin on each subsequent sclk. when chip-select is negated, miso pin is tri-stated. to allow sufficient time to reload the registers; chip-select pin shall remain negated for at least tcsn. the chip-select inputs have current sinks whic h pull these pins to the negated state when there is an open circuit condition. these pins have ttl level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply. serial clock (sclk) sclk input is the clock signal input for synchron ization of serial data transfer. this pin has ttl level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply. when ch ip select is asserted, both the spi master and l9659 will latch input data on the risi ng edge of sclk. the l9 659 shifts data out on the falling edge of sclk. serial data output (miso) miso output pins shall be in one tri-state condition when chip select is negated. when chip select is asserted, the msb is the first bit of the word/byte transmitted on miso and the lsb is the last bit of the word/byte transmitted. this pin supplies a rail to rail output, so if interfaced to a microprocessor that is using a lower vdd supply, the appropriate microprocessor input pin shall not sink more than ioh(min) and shall not clamp the miso output voltage to less than voh(min) while miso pin is in a logic ?1? state. when connecting to a micro using a lower supply, such as 3.3v, a resistor divider shall be used with high enough impedance to prevent excess current flow. table 9. features that are accessed/controlled for the spi function pin names features accessed squib diagnostic and deployment spi sclk miso mosi cs_d all squib diagnostics; squib related status information; squib arming and firing; software reset; component id & revision functional description l9659 22/51 doc id 022048 rev 2 serial data input (mosi) mosi inputs take data from the master processor while chip select is asserted. the msb shall be the first bit of each word/byte received on mosi and the lsb shall be the last bit of each word/byte received. this pin has ttl level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply. 3.4 squib drivers 3.4.1 firing the on-chip deployment drivers are designed to deliver 1.2a (min) for 2ms (min) and 1.75a (min) for 1ms (min)and 1.75a (min) for 0.65ms (min) with vresx voltages between 7v and 37v. in addition the l9659 can provide 1.5a minimum for 2ms for vresx voltages between 7v and 25v. the firing condition is selectable via the spi. at the end of a deployment, a deploy success flag is asserted and can be read using the appropriate spi command. each vresx and gndx connection is used to accommodate 8 loops that can be deployed simultaneously. upon receiving a valid deployment condition, the respective sqhx and sqlx drivers are turned on. the only other activation of the sqhx and sqlx drivers is momentarily during a mos diagnostic. otherwise, sqhx and sqlx are inactive under any normal, fault, or transient conditions. upon a successful deployment of the respective sqhx and sqlx drivers, a deploy command success flag is asserted via spi. refer to figure 8. for the valid conditions and the deploy success flag timing. the l9659 is protected against inadvertent turn on of the firing drivers unless the appropriate conditions are present. non-typical conditions will not cause driver activation. this includes the case where vresx and/or vsdiag pins are connected to a supply up to 40v and vdd is between 0v and vdd min. under these co nditions the l9659 will ensure that driver activation will not occur. no flow of current shall be a llowed through the sqhx and sqlx pins. l9659 functional description doc id 022048 rev 2 23/51 figure 7. deployment drivers diagram driver activation the firing of a squib driver requires the appropriate fen function to be active and two separate sixteen bit writes be made over the spi. the fen function is defined as the result of the fenx pin or?d with the internal fenx latch. the fenx pin going high initiates the fen function. with the fen 1 function bein g active and the appropriate arm and fire commands sent then squib_0 & 1 drivers would be activated. with the fen 2 function being active and the appropriate arm and fire commands sent then squib_2 & 3 drivers would be activated. with the fen 3 function being active and the appropriate arm and fire commands sent then squib_4 & 5 drivers would be activated. with the fen 4 function being active and the appropriate arm and fire commands sent then squib_6 & 7 drivers would be activated. the first write is to arm the drivers in preparation of receiving the fire command. the arm command will stop on all channel s any diagnostics that are active. any combination of squibs can be armed. the second write is a fire command that must directly follow the arm command and will activate the desired driver pairs assuming the fen function is valid. if there is a parity mismatch the data bits will be ignored and the squib drivers will not have their status changed, and the two write sequence must then be started again. if there is a mismatch in channels selected then only those channels selected in both the arm and fire commands will be activated. ' ! 0 ' 0 3 ' . $ 3 1 , 3 1 ( 6 2 % 3 ' . $ 3 1 , 3 1 ( 6 2 % 3 ' . $ 3 1 , 3 1 ( 6 2 % 3 ' . $ ' . $ 3 1 , 3 1 ( 6 2 % 3 6 2 % 3 ( 3 d r i v e r d i a g n o s t i c , 3 d r i v e r ( 3 d r i v e r d i a g n o s t i c , 3 d r i v e r ( 3 d r i v e r d i a g n o s t i c , 3 d r i v e r ( 3 d r i v e r d i a g n o s t i c d i a g n o s t i c , 3 d r i v e r , 3 d r i v e r ' . $ 3 1 , 3 1 ( 6 2 % 3 3 1 , 3 1 ( ( 3 d r i v e r d i a g n o s t i c , 3 d r i v e r ( 3 d r i v e r d i a g n o s t i c , 3 d r i v e r ( 3 d r i v e r d i a g n o s t i c , 3 d r i v e r ( 3 d r i v e r ' . $ 3 1 , 3 1 ( 6 2 % 3 ' . $ 3 1 , 3 1 ( 6 2 % 3 , o g i c ! n a l o g s q u i b r e s i s t a n c e m e a s u r e m e n t ! / 5 4 ) 2 % & ! ' . $ ' . $ 6 $ $ & % . & % . & % . & % . # 3 ? $ 3 # , + - / 3 ) - ) 3 / 6 3 $ ) ! ' functional description l9659 24/51 doc id 022048 rev 2 during the first write, when the drivers are armed, all diagnostic functions are cleared. the fire command must follow the arm command along with the fen function active for driver activation. if a command is between the arm and fire command then the sequence must be restarted. an error response will be rece ived for the fire command if the arm/fire sequence is not followed. the arm/fire commands and fen function are independent from each other. the l9659 will begin the t deploy timer once a valid arm/fire sequence has been received. if a valid arm/fire command has bee n sent and the fen fu nction is inactive then the drivers will not be activated but the t deploy timer will start. if the fen function becomes active before t deploy has expired then the drivers will become active for the full t deploy time. if the fen does not become active before t deploy has expired then the sequence would need to be restarted. a diagram illustrating this is shown in figure 8. figure 8. driver activation timing diagram only the channels selected in the arm and, directly following, the fire command will be able to be activated. by reading the appropriate registers a status of the deployment is provided. if a valid arm/fire sequence has been pr ovided the status flag will become active. this flag will remain active for as long as the t deploy timer is counting. depending on the state of the fen function the deploy_status flag will be active a minimum of t deploy and a maximum of 2 x t deploy . if driver activation did occur (both a valid arm/fire sequence and the appropriate fen function active within the appropriate time) then the deploy_success flag will be active following the completion of the driver activation period. this flag will be active until cleared by software. if a valid arm/fire sequence did occur but the fen function was never activated within the t deploy time then the deploy_success flag will remain ?0?. once the deploy success flag is set, it will inhibit the subsequent deployment command until a spi command to clear this deployment success flag is received. bits d7 through bit d0 are used to clear/keep the deploy success flag. when these bits are set to ?1,? the flag ' ! 0 ' 0 3 3 0 ) # o m m a n d s & % . & u n c t i o n $ r i v e r ! c t i v e 4 i m e 4 $ % 0 , / 9 4 $ % 0 , / 9 ! & ! ! & ! ! r m # o m m a n d $ e p l o y m e n t - o d e & & i r e # o m m a n d $ e p l o y m e n t - o d e 4 $ % 0 , / 9 $ % 0 , / 9 ? 3 4 ! 4 5 3 & l a g 4 $ % 0 , / 9 $ % 0 , / 9 ? 3 5 # # % 3 3 & l a g l9659 functional description doc id 022048 rev 2 25/51 can be cleared. otherwise, the state of these flags is not affected. the success flag must be cleared to allow re-activation of the drivers. during driver activation the respective high side (sqhx) and low side (sqlx) drivers will turn on for t deploy . l9659 driver activation will not occur or, if firing is in process, will terminate under the following conditions: power on reset (por) iref resistance is larger than riref_h or smaller than riref_l loss of ground condition on gnd pin the following conditions are ignored when driver activation is in-progress: resetb valid soft reset sequences spi commands except as noted below. response for ignored commands will be 0xd009 fen function the following table shows the response when sending spi commands during deployment. note 1: spi miso sent in the next spi transmission. the l9659 can only deploy a channel when the fen function is active. once the drivers are active the l9659 will keep the drivers on for the required duration re gardless of the fen state. once complete a status bit will be set to indicate firing is complete. 3.4.2 firing current measurement all channels have a 7 bit current measurement register that is used to measure the amount of time the current is above i meas during firing. the maximum measurement for each channel is 3.175ms nominal based on a bit weight of 25s. the current measurement register will not increment ou tside the deployment time. the current measurement will begin incrementing once the current has exceeded 95% of the nominal target value. the count will continue to increment from the stored value until either a clear command has been issued for that channel or all ?1?s are present in the corresponding channel measurement register. if all ?1?s are present for a channel?s measurement register and another firing sequence has been issued the register will remain all ?1?s. only if a clear command has been issued will that particular register be reset to all ?0?s. all other channels shall keep the stored measurement count. during firing the current measurement register cannot be cleared. after a clear command has been issued for a channel then the channel is ready to count if table 10. spi mosi/miso response spi mosi spi miso response configuration commands spi fault response mosi regist er mode messages will be ignored deployment commands command mode execute for channels not in deployment; no effect to deploying channel diagnostic commands spi fault response mosi diagnostic mode messages will be ignored monitor commands status response execute for all channels functional description l9659 26/51 doc id 022048 rev 2 the current exceeds the specified level. after a por or software reset the l9659 will reset all 8 measurement registers to all ?0?s. a ?real-time? current measurement status of all the channels is available. if a current limit status request is sent then the l9659 will re port in the next spi tran sfer whether the current is above or below imeas for each of the channels. the current status re sults can be read at any time and will correctly report whether current is flowing. the content of the internal current status register is captured on the falling edge of chip select during the spi response. the internal status register is updated at a nominal sample time of 25s and is independent of spi transfers. for this circuit there is continuously being performed compensation of the comparator to remove offset errors, which is independent from spi commands. the compensation is being performed every 12.8s based on the internal clock. 3.4.3 fire enable (fen) function description the fire enable (fen) function is the result of the fenx input or?d with the internal fen latch. if the fen latch is not enabled and the fenx pin is low then activation of the fet drivers are disabled except as indicated during the mos test. all internal diagnostic functions, and results, will be available through the serial interface. this pin must be pulled high to initiate the fen latch function (if programmed) and enable firing of the fet drivers. there are four fen function blocks fen function 1 is fen1 input or?d with fen1 latch timer and used for enabling channels 0 & 1 fen function 2 is fen1 input or?d with fen2 latch timer and used for enabling channels 2 & 3 fen function 3 is fen1 input or'd with fen3 latch timer and used for enabling channels 4 & 5 fen function 4 is fen1 input or'd with fen4 latch timer and used for enabling channels 6 & 7 the fen function will be considered active when the pin is active (?1? or high) for more than 12 microseconds. tolerance range for the filter used is 12 to 16 secs. when the fenx input is active, ?1?, the fen function will be active. when the fenx input state transitions from ?1? to ?0?, the programmable latching function will hold the fen function active until the timeout of the fen timer. the programmable latch and hold function will be capable of delays of 0m s, 128 ms, 256 ms, and 512 ms. there are 4 independent timers with the timer for fen1 associated with channels 0 & 1, timer for fen2 associated with channels 2 & 3, timer for fen3 associated with channels 4 & 5, timer for fen4 associated with channels 6 & 7. the timer is reset to th e programmed time when the fenx pin transitions from ?0? to ?1?. the programmable counter delay will be set through a spi command. l9659 functional description doc id 022048 rev 2 27/51 3.4.4 squib diagnostics overview the asic is able to perform the following diagnostics short to battery and ground on both sqhx and sqlx pins with or without a squib loop to loop diagnostics squib resistance measurement squib high resistance high side safing fet diagnostics vresx voltage status high and low side fet diagnostics below is a block diagram showing the components involved in the squib diagnostics. figure 9. squib diagnostics block diagram short to battery/ground and loop to loop diagnostics the leakage diagnostic includes a short to battery, a short to ground and a short between loop tests. the test will be run for each sqhx and sqlx pin so that shorts can be detected regardless of the resistance between the squib pins. normal short to battery/ground diagnostics. for the test the internal vrcm is switched on and connected to the selected pin (sqhx or sqlx) pin. the ipd bit will be selected to be o ff which will deactivate the pulldown current ' ! 0 ' 0 3 6 2 % 3 6 2 % 3 x 3 1 ( 3 1 ( x 3 1 , x ' . $ x n 3 1 , ' . $ n 3 e l ) 0 $ 3 e l ) 0 $ ) 3 ) . + 3 e l ' 3 e l " 3 e l ! ) 3 2 # & 3 e l 2 ( 3 3 6 3 $ ) ! ' # 3 e l # 3 e l # a l ! / 5 4 ' a i n 6 o l t 3 ' 3 " , ( 3 2 3 " m i r r o r m i r r o r 6 2 # - b l o c k ) 3 2 # ? ( 3 3 3 e l % ' . $ $ 3 e l ( 3 3 s h o r t ( 3 3 o p e n ( i g h s i d e 3 a f i n g d i a g n o s t i c c o m p 3 q u i b r e s i s t a n c e d i a g n o s t i c 3 h o r t t o " a t t e r y ' r o u n d ( i g h s q u i b r e s i s t a n c e d i a g n o s t i c s 6 2 % 3 x , / 6 2 % 3 x ( ) c o m p 6 t h ? ( 6 t h ? , 6 o l t a g e m e a s u r e m e n t d i a g n o s t i c n 2 s q u i b 3 e l % # , + ? ( 3 3 c o m p 6 2 % 3 6 2 % 3 x 3 1 ( 3 1 ( x 3 1 , x ' . $ x n n 3 1 , ' . $ n n 3 e l 3 e l ) 0 $ 3 e l 3 e l ) 0 $ ) 3 ) . + 3 e l ' 3 e l " 3 e l ! ) 3 2 # & 3 e l 2 ( 3 3 6 3 $ ) ! ' # 3 e l # 3 e l # a l ! / 5 4 ' a i n 6 o l t 3 ' 3 " , ( 3 2 3 " m i r r o r m i r r o r 6 2 # - b l o c k ) 3 2 # ? ( 3 3 3 e l % ' . $ $ 3 e l ( 3 3 s h o r t ( 3 3 o p e n ( i g h s i d e 3 a f i n g d i a g n o s t i c c o m p 3 q u i b r e s i s t a n c e d i a g n o s t i c 3 h o r t t o " a t t e r y ' r o u n d ( i g h s q u i b r e s i s t a n c e d i a g n o s t i c s 6 2 % 3 x , / 6 2 % 3 x ( ) c o m p 6 t h ? ( 6 t h ? , 6 o l t a g e m e a s u r e m e n t d i a g n o s t i c n 2 s q u i b 3 e l % # , + ? ( 3 3 c o m p functional description l9659 28/51 doc id 022048 rev 2 on the channel under test and all other channels. during the test with no leakage present the voltage on the selected sqhx or sqlx pi n will be equal to vbias and no current is sunk or sourced by vrcm. if a leak age to ground, battery or to sqly is present, the vrcm will sink or source a current less then i svrcm trying to keep vbias. two current comparators, istb and istg, will detect th e abnormal current flow. loop to loop diagnostics for this test the same procedure is followed except the pulldown current (ipd) is selected to be on which will deactivate the pulldown current only on the channel under test with all other channel pulldown currents active. if a short to ground fault is active, assuming it was not active during normal short to battery/ground diagnostics, then that particular channel has a short to another squib loop. to detect loop to loop shorts between asics in the system the stop diagnostics command with ipd enabled needs to be sent to the other asics before running the loop to loop diagnos tics on the channel to be monitored. if the channel being monitored has a short to ground fault active, assuming it was not active during normal short to battery/ground diagnostics, then that particular channel has a short to another squib loop in the system. the following table indicated how faults would be interpreted. once the command is issued t he state of the comparators will be captured on the next falling edge of cs_d. the results are valid after t shortdiag time, which is mainly dependant on the external capacitors on the squib lines. squib resistance measurement during a resistance measurement, both isrc and isink are switched on and connected to the selected sqhx and sqlx channel. a differ ential voltage is created between the sqhx and sqlx pin based in the isrc current and resistance between the pins. the analog output pin, aout, will provide the resistan ce-measurement voltage based on the scaling factor indicated in the electrical parameters section. the tri-state output, aout, will be connected to an adc input of a microprocessor. when not running squib resistance diagnostics the aout pin will be high impedance. to increase accuracy of the squib resistance measurements the offset of the internal amplifier can be provided on the aout pin. this is done by setting the appropriate calibration bit, waiting the required time, and reading the converted aout voltage connected to the microprocessor adc. the normal measurement method for squib resistance is to take a single ended analog output measurement for a channel (v aout with amc bit=0) and use the tolerances and table 11. how faults shall be interpreted fault condition for channel (1) 1. condition where 4 open channels have the sqhx pins shorted will not be detected. if one squib is open and the other has a normal squib connection then the faul t will be indicated on the channel that is open. assumes both pins are tested channel leakage diagnostics results with i pd on channel leakage diagnostics results with i pd off no shorts no fault no fault short to battery stb fault stb fault loop to loop short stg fault no fault short to ground stg fault stg fault l9659 functional description doc id 022048 rev 2 29/51 equation shown in the parametric table. the l9659 is also capable of improving the tolerance at resistances below 3.5 ohms by removing the offset of the differential comparator. this method works taking the single ended analog output results for a channel (v aout with amc bit=0) and subtracting the internal comparator offset measurement of v aout_cal (v aout with amc bit=1). the summary of the equation for this is as follows: a out_cal = (v aout ? v aout_cal )/vdd a out_cal typical = 0.08 x r squib high squib resistance diagnostics during a high squib resistance diagnostic, vrcm and isink are switched on and connected to sqhx and sqlx on the selected channel. cu rrent flowing on sqhx will be measured and compared to ihr threshold to identify if resistance is above or below rsqhz. the results will be reported in the next spi message. once the command is issued the state of the squib resistance will be valid a fter thsr captured on th e next falling edge of cs_d. the voltage source for this test will be vbias which is based on the vdd supply. a way to reduce the time required until valid results are available is to perform a leakage diagnostics prior to this test. the leakage dia gnostics will bias the volt age on the squibs to around 3.5v, which is the same bias voltage required for the high squib resistance diagnostic. by following running this sequence of diagnostics will reduce the test time to from 1.5ms to 200s. high and low side fet diagnostics prior to either the hs or ls fet diagnostic s being run it is required to have the vrcm switched on. running the leakage diagnostics with the appropriate delay time prior to either the hs or ls fet diagnostics can do this. when the fet diagnostic command is issued the flags will initially be cleared. if the vrmc is not active or some leakage is present then the mos will not be turned on, the test will be abo rted and fault present (fp) bit will be set. the fen function must be inactive to run test. the test will not start if fen function is active on channel under test and it will result in the fault present (fp) bit to set. if no leakage is present and fen function is inactive, the mos (high side or low side) is turned on. the l9659 will monitor the current sink or sourced by vrcm. if the mos is working properly, this current will exceed istb (hs test) or istg (ls test) and the l9659 will turn off the driver under test within the specified time t shutoff . if the current does not exceed istb or istg then th e test will be terminated and the mos will be switched off by the l9659 within t fettimeout . during the t fettimeout period the fet timeout bit will be set (ft=1) and will be cleared at the expiration of the timer. the results must be compared with the leakage diagnostic results to distinguish between a real leakage/short versus a fet fault. for hi gh side fet diagnostics if no faults were indicated in the preceding leakage diagnostics then a normal result would be stb=1;stg=0 (with ft=0;fp=0). if the returned results for the high side fet test is not stb=1;stg=0 (with ft=0;fp=0) then either the fet is not functional, a short occurred during the test, or there is a missing vresx connection for that channel. for low side fet diagnostics if no faults were indicated in the preceding leakage diagnostics then a normal result would be stb=0;stg=1 (with ft=0;fp=0). if the returned results for the low side fet test is not stb=0;stg=1 (with ft=0;fp=0) then either the fet is not functional, a short occurred during the test, or there is a missing gndx connection for that channel. if the test is in progress then a bit (ft) is used in the response to indicate this status. once the command is issued, output of comparators will be latched. functional description l9659 30/51 doc id 022048 rev 2 on the next falling edge of cs_d, comparator latched data are captured and reported to miso response. the result s will remain latch until the next te st is initiated (diagnostic write command). if the test is in progress then a bit is used in the response to indicate the test completion. if the fet under test is working prop erly then the results will indicate a ?short to ground? for ls test and ?short to battery? for hs test. if a leakage is present prior to the test or fenx is asserted then both ?short to gr ound? and short to battery? will be indicated in the response for either a ls or hs fet test. for all conditions the current on sqhx/sqlx will never exceed i svrcm . on the squib lines there will be highertransient cu rrents due to the presence of the filter capacitor. high side safing diagnostics when the command is received the l9659 will activate ihss on the selected vresx. the diagnostics will measure the difference be tween vsdiag and vresx. the internal comparator will detect open, short or normal condition base d on the differential voltage between vsdiag and vresx. the results will be reported in the next sp i message using bits hss1 and hss0 as indicated in the following table. once the co mmand is issued the voltages will be captured on the next falling edge of cs_d. voltage measurement diagnostics (vresx) when the command is receiv ed the l9659 will activate a co mparator for the selected channel. a 2 bit indication of the state of the vresx pins will be reported as indicated below. the results will be reported in the next sp i message. once the command is issued the voltages will be captured on the next falling edge of cs_d. loss of power ground when any of the power grounds (gnd0 ? 7) are lost, no deployment can occur on the respective deployment channel s because the low side driver will be inactive. the high side driver for the respective channel can still be activated. a loss of ground condition on one or several channels will not affect the operatio n of the remaining channels. when a loss of ground condition occurs, the source of the low side mos will be floating. in this case, no current will flow through the low side driver. table 12. diagnostic mode hss selection condition hss1 hss0 ( vsdiag-vresx) < v hssshort_th 0 0 v hssshort_th < (vsdiag-vresx) < v hssopen_th 0 1 v hssopen_th < (vsdiag-vresx) 1 1 table 13. diagnostic mode 3 vresx selection condition vr1 vr0 v resx < v vresxlo_th 0 0 v vresxlo_th < v resx < v vresxhi_th 0 1 v vresxhi_th < v resx 1 1 l9659 functional description doc id 022048 rev 2 31/51 this condition will be dete cted as a fault by a low side mos diagnostic. no additional faults will be reported from any other diag nostic due to this condition. 3.4.5 spi register defi nition for squib functions the spi provides access to read/write to the registers internal to the l9659. all commands and responses sent to/from the l9659 on spi will use set d13 as required for odd parity on the 16 bit word. the responses to the commands are sent in the next valid cs_d. the table below summarizes the miso register mode response of various events and mosi messages. after por ev ent, resetb negated, a nd loss of gnd, the l9659 sends 0x0000 in miso for the first spi transmission. the miso response shown here is the one received in the next valid spi transmission after each event or mosi write. note: x in software reset response interpreted as follows: d11=1;d10=0;d9:d8=cl bits the spi fault responses (0xd000 or 0xd003) indicate a fault in the last mosi transmission. the l9659 uses the parity bit to determine the integrity of the mosi command transmission. table 14. miso responses to various events event/mosi messag e miso response mosi parity error or unrecognized command 0xd000 mosi transmission - incorrect number of clocks/bits 0xd003 incorrect firing sequence received (firing command without a valid arm command) 0xd005 error due to message not allowed during deployment 0xd009 por 0x0000 resetb 0x0000 loss of gnd 0x0000 riref out of range 0x0000 mosi write soft reset: $aa 0x1x02 mosi write soft reset: $55 (after $aa) 0x2003 functional description l9659 32/51 doc id 022048 rev 2 3.4.5.1 squib spi commands the following are the modes that are supported by the squib l9659 using spi. configuration mode deployment mode diagnostic mode monitor mode the table below is a summary of the modes and the functions that are achieved be sending the particular mosi command. the following se ctions will provide a full description of bit settings for each mode. all commands and responses use d13 to achieve odd parity. the squib circuits can be reset over when sending the appropriate configuration commands via spi. table 15. command description summary command/mode description mode bits d15 d14 d13 d12 d11 d10 d09 d08 d07 - d00 configuration commands config. mode 1 current limit programming and software reset 00p - -0 - - - config. mode 2 fen latch time programming 0 0 p - - 1 - - - deployment commands deployment mode 1 arming command 0 1 p 11001 - deployment mode 2firing command 01p00000 - diagnostic commands diagnostic mode 1 disable diagnostic 1 0 p - 0 0 0 - - diagnostic mode 2 short to battery & ground diagnostics short between loop diagnostics 10p -001 - - diagnostic mode 3 vresx voltage diagnostics 1 0 p - 0 1 0 - - diagnostic mode 4 high side safing diagnostics 1 0 p - 0 1 1 - - diagnostic mode 5 squib resistance diagnostics 1 0 p - 1 0 0 - - diagnostic mode 6 high squib resistance diagnostics 1 0 p - 1 0 1 - - diagnostic mode 7 ls driver diagnostics 1 0 p - 1 1 0 - - diagnostic mode 8 hs driver diagnostics 1 0 p - 1 1 1 - - monitor commands monitor mode 1 deployment status 1 1 p - 0 0 - - - monitor mode 2 channel current limit measurement information 11p -01 - - - monitor mode 3 fenx function status and active current limit status 11p -10 - - - monitor mode 4 revision and l9659 id 1 1 p - 1 1 - - - p = parity bit ? all commands and responses will use this bit to achieve odd parity l9659 functional description doc id 022048 rev 2 33/51 configuration commands configuration mode 1 configuration mode 1 main functions are as follows: set deployment current for all channels. a ll channels will be either set to 1.2a/2ms, 1.5a/2ms (maximum vresx voltage limited to 25v) 1.75a/1ms or 1.75a/0.65ms perform a software reset the spi message definition for mosi commands and miso responses in this mode are defined below. bit [d9:d8] bits used to set the firing current/time for all channels. the default state is ?00? (1.2a/2ms min.) bits [d7:d0] the soft reset for the l9659, which includes deployment driver/diagnostics, is achieved by writing 0xaa and 0x55 within two msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mosi command for configuration mode 1 0 0 p r/w swr 0 cl set bits software reset sequence bits miso response for configuration mode 1 (except for soft reset/d11 =1 and appropriate pattern) 0 0 p r/w swr 0 cl set bits 0 0 0 0 0 0 1 0 table 16. configuration mode 1 bit mosi command miso response state description d15 0 mode bits see above d14 0 see above d13 odd parity ? includes all 16 bits odd parity ? includes all 16 bits d12 0 read (default) - when d12=?0? bits d11 to d0 are ignored r/w bit 1 write ? allows soft reset and deployment programming d11 0 sets deployment condition for all channels - when d11=?0? bits d7 to d0 are ignored see above 1 soft reset sequence ? bits d8 and d9 are ignored d10 0 see above d9 sets deployment conditions 00 = 1.2a/2ms (default) 01 = 1.5a/2ms 10 = 1.75a/0.65ms 11 = 1.75a/1ms internal stored value cl bits d8 - d7 ? d2 software reset-sequence see above d1 see above d0 see above functional description l9659 34/51 doc id 022048 rev 2 subsequent 16-bit spi transmissions. if the sequence is broken, the processor will be required to re-tr ansmit the sequence . the l9659 will not reset if the sequence is not completed within two subsequent 16- bit spi transmissions. when soft reset command is received, the l9659 reset its deployment driver?s internal logic and timers, including all internal registers. the effects of a soft reset is the same as a of por event, except miso response. bit [d1] first response after por (or equivalent) the pu bit is set to ?0?. all responses following the bit is set to ?1?. bit [d0] bit d0 used to report the soft reset sequence status. if valid soft reset sequences are received, bit d0 is set to ?1.? otherwise, bit d0 is set to ?0.? when l9659 receives valid soft reset sequences, it will send a miso configuration mode response containing 0x2003 in the next spi transmission. configuration mode 2 configuration mode 2 main function is as follows: set the latch time for fenx input the spi message definition for mosi commands and miso responses in this mode are defined below. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mosi command for configuration mode 2 0 0 p r/w 0 1 latch bits 0 0 0 0 0 0 0 0 miso response for configuration mode 2 0 0 p r/w 0 1 latch bits 0 0 0 0 0 0 0 0 table 17. configuration mode 2 bit mosi command miso response state description d15 0 mode bits see above d14 0 see above d13 odd parity ? includes all 16 bits odd parity ? includes all 16 bits d12 0 read (default) - when d12=?0? bits d11 to d0 are ignored r/w bit 1 write ? fen latch programming - d11 0 - - d10 1 - - l9659 functional description doc id 022048 rev 2 35/51 bits [d9:d8] bits are used to set the period of the fen latch timer. the l9659 has 4 independent time rs. a valid fenx input will start the pulse stretch timer. these bits will set the timer duration. these values default to ?00? after a por event. deployment commands the deployment mode is used to activate the drivers. two consecutive commands are required to activate the drivers. any combination of channels can be fired as long as the prerequisite conditions are met as indicated in the previous section. the spi message definition for mosi commands and miso responses in deployment mode are defined below. d9 - fen latch time 00 = 0ms (default) 01 = 128ms 10 = 256ms 11 = 512ms internal stored value fen latch bits d8 d7 ? d0 0 - see above table 17. configuration mode 2 bit mosi command miso response state description msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mosi command for deployment mode 1 0 1 p 1 1 0 0 1 0 0 0 0 arming channel select miso response for deployment mode 1 0 1 p 1 1 0 0 1 0 0 0 0 armed channels mosi command for deployment mode 2 0 1 p 0 0 0 0 0 0 0 0 0 firing channel select miso response for deployment mode 2 0 1 p 0 0 0 0 0 0 0 0 0 channels activated or channels waiting for fen input table 18. deployment mode 1 bit definition bit mosi command miso response state description d15 0 mode bits see above d14 1 see above d13 - odd parity ? includes all 16 bits odd parity ? includes all 16 bits d12 ? d8 - arm pattern see above functional description l9659 36/51 doc id 022048 rev 2 d7 0 channel 7 idle (default) internal stored value arm bit 1 arm channel 7 d6 0 channel 6 idle (default) internal stored value arm bit 1 arm channel 6 d5 0 channel 5 idle (default) internal stored value arm bit 1 arm channel 7 d4 0 channel 4 idle (default) internal stored value arm bit 1 arm channel 4 d3 0 channel 3 idle (default) internal stored value arm bit 1 arm channel 3 d2 0 channel 2 idle (default) internal stored value arm bit 1 arm channel 2 d1 0 channel 1 idle (default) internal stored value arm bit 1 arm channel 1 d0 0 channel 0 idle (default) internal stored value arm bit 1 arm channel 0 table 19. deployment mode 2 bit definition bit mosi command miso response state description d15 0 mode bits see above d14 1 - see above d13 - odd parity ? includes all 16 bits see above d12 ? d8 - fire pattern see above d7 0 channel 7 idle (default) internal deploy status 1 deploy channel 7 d6 0 channel 6 idle (default) internal deploy status 1 deploy channel 6 d5 0 channel 5 idle (default) internal deploy status 1 deploy channel 5 d4 0 channel 4 idle (default) internal deploy status 1 deploy channel 4 d3 0 channel 3 idle (default) internal deploy status 1 deploy channel 3 table 18. deployment mode 1 bit definition (continued) bit mosi command miso response state description l9659 functional description doc id 022048 rev 2 37/51 the deploy status becom es ?1? when there is a valid fire sequence. once active it will become ?0? when the time out has expired waiting fen activation or when squib driver has turned off for fire completion. the same information is available when receiving a response from monitor mode 1. for the drivers to be fire capable the command mode 1 (arming) must be sent followed by command mode 2 (firing). with this sequence valid and fen active then firing will begin. a break in the sequence will require the process to be restarted. all other bit patterns for d12- d8 wil be ignored and the l9 659 will respond with $d005. to begin a deployment 2 consecutive commands need to be sent along with the fen active (external or internal latch). an example of a firing sequence for channel 0 would be as follows fenx active or inactive tx ? 0x5901 ? arm channel 0 rx ? based on previous command tx ? 0x5901 ? arm channel 0 rx ? 0x5901 tx ? 0x5901 ? arm channel 0 rx ? 0x5901 tx ? 0x6001 ? firing on channel 0 is started on if fen is active rx ? 0x5901 tx ? 0x6001 ? command ignored ? sequence is not allowed rx ? 0x6001 tx ? 0x6001 ? command ignored rx ? 0xd005 alternatively, if the sequence is broken th e response will be as in the following example fenx active tx ? 0x5901 ? arm channel 0 rx ? based on previous command tx ? 0x2000 ? read of register mode 1 rx ? 0x5901 tx ? 0x6001 ? command ignored ? sequence is not allowed rx ? contents of register d2 0 channel 2 idle (default) internal deploy status 1 deploy channel 2 d1 0 channel 1 idle (default) internal deploy status 1 deploy channel 1 d0 0 channel 0 idle (default) internal deploy status 1 deploy channel 0 table 19. deployment mode 2 bit definition bit mosi command miso response state description functional description l9659 38/51 doc id 022048 rev 2 tx ? 0x6001 ? command ignored ? sequence is not allowed rx ? 0xd005 if, for example, channel 0 and 1 bits are set in the arm command and channel 0 and 7 bits are set in the fire command th en the result will be the drivers on channel 0 will be activated (assuming fen function is active) a nd there will be no ef fect on channel 7. during a deployment, any commands directed to the channel that are in deployment are ignored and the response shall be 0xd009. diagnostic commands diagnostic mode diagnostic mode main functions are as follows: squib short to battery/ground diagnostics loop to loop diagnostics normal squib resistance diagnostics high squib resistance diagnostics high side safing diagnostics vresx measurement ls and hs fet test the spi message definition for mosi commands and miso responses in diagnostic mode are defined below. l9659 functional description doc id 022048 rev 2 39/51 write commands definition read commands definition bits d13 parity bit. command and response will use odd parity bits d12 r/w 1 = write (execute command) 0= read for bits d11:d09 the following table shall be used for diagnostic selection. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mosi command for diagnostic mode execution 1 0 p 1 diag. selection bits 0 0 0 sqp ipd_dis amc channel selection miso response for diagnostic mode, stop diagnostic selection (mosi d11:d9=000) diagnostic mode 1 1 0 p 1 0 0 0 0 0 0 0 ipd_dis 0 000 miso response for short to ba ttery/ground selection (mosi d1 1:d9=001) diagnostic mode 2 1 0 p 1 0 0 1 stb stg 0 sqp ipd_dis 0 channel selection miso response for diagnostic mode, vresx sel ection (mosi d11:d9=010) diagnostic mode 3 1 0 p 1 0 1 0 vr1 vr0 0 0 ipd_dis 0 channel selection miso response for diagnostic mode, high side safing selection (mos i d11:d9=011) diagnostic mode 4 1 0 p 1 0 1 1 hss1 hss0 0 0 ipd_dis 0 channel selection miso response for diagnostic mode, squib resistance selection (mosi d11:d9=100) diagnostic mode 5 1 0 p 1 1 0 0 0 0 0 0 ipd_dis amc channel selection miso response for diagnostic mode , high squib resistan ce selection (mosi d11:d9=101) diag. mode 6 1 0 p 1 1 0 1 hsr 0 0 0 ipd_dis 0 channel selection miso response for diagnostic mode, low side fet test selection (mosi d11:d9=110) diagnostic mode 7 1 0 p 1 1 1 0 stb stg fp ft ipd_dis 0 channel selection miso response for diagnostic mode, high side fet t est selection (mosi d11:d9 =111) diagnostic mode 8 1 0 p 1 1 1 1 stb stg fp ft ipd_dis 0 channel selection msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mosi command for diagnostic mode, read command 1 0 p 0 0 0 0 1 1 1 1 0 0 000 miso response for diagnostic mode, read command 1 0 p 0 diag. selection bits internal state x x x x ipd_dis x channel selection internal state functional description l9659 40/51 doc id 022048 rev 2 bits d8:d7 the definition of the resp onse bits will change as follows based on diagnostic select stb/stg bit definition with mo si d11:d9=001 (leakage test) stb bit bit used for indicating leakage to battery. 0 = no leakage to battery 1 = short to battery / hs driver test pass stg bit bit used for indicating leakage to ground. 0 = no leakage to battery 1 = short to ground / ls driver test pass stb/stg bit definition with mosi d11:d9=110 (ls fet) stb, stg bits see table below table 20. diagnostic selection diagnostic bits current source active comparator or amplifier d11 d10 d9 stop diagnostic 0 0 0 no no short to battery/ground and short between loops 0 0 1 y (vmrc) y (comp istb/istg) vresx diagnostic 0 1 0 n y (comp vresx) high side safing diagnostics 0 1 1 y (ihss) y (comp hss) squib resistance diagnostics 1 0 0 y (isrc/isink) y (ampli ) high squib resistance diagnostics 1 0 1 y (vmrc/isink) y (comp ihr) ls fet test 1 1 0 y (vmrc) y (comp istb/istg) hs fet test 1 1 1 y (vmrc) y (comp istb/istg) table 21. diagnostic mode ls fet selection condition stb stg test in process (ft=1); fault present prior to run test (fp=1); or ls fet/gndx open fault (fp=0,ft=0). on ly valid if test is in process or inactive. 0 0 short to battery occurred during test. 1 0 test pass if leakage diagnostics did not indicate a short to gnd. 0 1 l9659 functional description doc id 022048 rev 2 41/51 stb/stg bit definition with mosi d11:d9 =111 (hs fet) stb, stg bits see table below hss1:hss0 bit definition with mosi d11:d9=011 (high side safing) hss1:hss0 bits see table below vr1:vr0 bit definition with mosi d1 1:d9=010 (vresx supply voltage) vr1:vr0 bits see table below hsr bit definition with mosi d11: d9=101 (high squib resistance) hsr bit bit used for indicating a high squib resistance. 0 = squib resistance below r sqhiz 1 = squib resistance above r sqhiz bits d6 fp fault present prior to running ls fet or hs fet test (diagnostics aborted) 0 = normal 1 = test not run - fault present (fen in incorrect state, short to battery or ground) bits d5 bit definition based on diagnostic selection. ft bit read only - used for ls fet or hs fet diagnostics and is the status of the fet timer 0 = fet timer not active 1 = fet timer active table 22. diagnostic mode hs fet selection condition stb stg test in process (ft=1); fault presen t prior to run test (fp=1); or hs fet/vresx open fault (fp=0,ft=0). only valid if test is in process or inactive. 0 0 test pass if leakage diagnostics did not indicate a short to battery. 1 0 short to ground occurred during test. 0 1 table 23. diagnostic mode hss selection condition hss1 hss0 (vsdiag-vresx) < v hssshort_th 0 0 v hssshort_th < (vsdiag-vresx) < v hssopen_th 0 1 v hssopen_th < (vsdiag-vresx) 1 1 table 24. diagnostic mode vresx selection condition vr1 vr0 v resx < v vresxlo_th 0 0 v vresxlo_th < v resx < v vresxhi_th 0 1 v vresxhi_th < v resx 1 1 functional description l9659 42/51 doc id 022048 rev 2 sqp bit: squib pin to be tested during short to battery/ground diagnostics 0 = sqblx pin test 1 = sqbhx pin test bits d4 used to disable ipd on all channels 0 = ipd active as indicated; ? active for all channels except the one under test when running short to battery/ground and short between loops diagnostics and ls/hs fet test ? active for all channels when running stop diagnostic, resistance diagnostics, high squib resistance diagnostics, hss diagnostic and vresx diagnostics 1 = ipd disabled on all channels bits d3 amc bit bit used for resistance measurement amplifier calibration. only valid when squib resistance diagnostics is selected, otherwise this it will be ignored and a 0 will be reported in the response 0 = no calibration (normal squib resistance measurements) 1 = calibration for bits d2:d0 the following table shall be used for channel selection. all other combinations for mosi bits d2:d0 will produce an error response of 0xd000. note: except for short to battery /g round diagnostics and loop to loop test the state of ipd (d4) will not affect the test. table 25. channel selection channel bit d2 bit d1 bit d0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 41 0 0 51 0 1 61 1 0 71 1 1 l9659 functional description doc id 022048 rev 2 43/51 monitor commands monitor mode 1 monitor mode main information: deployment status the spi message definition for mosi commands and miso responses in monitor mode 1 are defined below. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mosi command for monitor mode 1 1 1 p 0 0 0 0 ds channel selection status request miso response for monitor mode 1 1 1 p 0 0 0 0 ds channel status table 26. mosi diagnostic mode 1 bit definition bit mosi command miso response state description d15 1 mode bits see above for state d14 1 see above for state d13 odd parity ? includes all 16 bits odd parity ? includes all 16 bits d12 0 - see above for state d11 0 monitor mode selection bits see above for state d10 0 monitor mode selection bits see above for state d9 0 - see above for state d8 0 report deploy success flag (default) internal state of report setting 1 report deploy status d7 0 keep deploy success flag channel 7 (default) deploy information for channel based on bit d8 will either be deploy_status7 or deploy_success7 1 clear deploy success flag channel 7 d6 0 keep deploy success flag channel 6 (default) deploy information for channel based on bit d8 will either be deploy_status6 or deploy_success6 1 clear deploy success flag channel 6 d5 0 keep deploy success flag channel 5 (default) deploy information for channel based on bit d8 will either be deploy_status5 or deploy_success5 1 clear deploy success flag channel 5 d4 0 keep deploy success flag channel 4 (default) deploy information for channel based on bit d8 will either be deploy_status4 or deploy_success4 1 clear deploy success flag channel 4 d3 0 keep deploy success flag channel 3 (default) deploy information for channel based on bit d8 will either be deploy_status3 or deploy_success3 1 clear deploy success flag channel 3 functional description l9659 44/51 doc id 022048 rev 2 the deploy_successx flag indicates if th e corresponding channel?s drivers were activated and that the activation period has completed. this bit is set when the activation period has expired. the deploy_successx flag will be ?1? until it is cleared by writing a ?1? to the appropriate channel(s) (bits d7-d0). the deploy_statusx bit will become ?1? when th ere is a valid arm and fire sequence for the corresponding channel. the deploy_statusx bit transitioning from a ?0? to a ?1? does not depend on the state of th e fen function. it will become ?0 ? when time out has expired. depending on the state of fen the deploy_statusx flag could be ?1? for a minimum of 1x t deploy and a maximum of up to 2 x t deploy (see figure 8. ). the deployment status is captured on the falling edge of cs_d. bit d8 is used to select the meaning of bit d7 through bit d0 in the status response message. when this bit is set to ?1,? bits d7 through d0 in the stat us response message will report the state of the deploy_statusx flag. when this bit is ?0,? bit d7 through bit d0 in the status response message will report the deploy_successx flag. the following ta ble shows the conditions for the deploy_statusx flag and the deploy_successx flag. once the deploy success flag is set, it will inhibit the subsequent deployment command until a spi command to clear this deployment success flag is received. bits d7 through bit d0 are used to clear/keep the deploy success flag. when these bits are set to ?1,? the flag can be cleared. otherwise, the state of these flags is not affected. the success flag must be cleared to allow re-activation of the drivers d2 0 keep deploy success flag channel 2 (default) deploy information for channel based on bit d8 will either be deploy_status2 or deploy_success2 1 clear deploy success flag channel 2 d1 0 keep deploy success flag channel 1 (default) deploy information for channel based on bit d8 will either be deploy_status1 or deploy_success1 1 clear deploy success flag channel 1 d0 0 keep deploy success flag channel 0 (default) deploy information for channel based on bit d8 will either be deploy_status0 or deploy_success0 1 clear deploy success flag channel 0 table 26. mosi diagnostic mode 1 bit definition bit mosi command miso response state description table 27. deploy_statusx flag and th e deploy_successx flag conditions deploy_statusx flag deploy _successx flag description 0 0 no deployment in process or has been initiated since por or since last clear of success flag 0 1 deployment has successfully completed 1 0 deployment in process 1 1 deployment terminated / lsd shutdown l9659 functional description doc id 022048 rev 2 45/51 monitor mode 2 monitor mode main information: current limit measurement of channels the spi message definition for mosi commands and miso responses in monitor mode 2 are defined below. bits [d9:d7]. used when sending the mosi command to select the channel to be measured. the miso response will echo the mosi command. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mosi command for monitor mode 2 1 1 p clr 0 1 current measurement channel select 0 0 0 0 0 0 0 miso response for monitor mode 2 1 1 p 0 0 1 current measurement channel current measurement data table 28. mosi monitor mode 2 bit definition bit mosi command miso response state description d15 1 mode bits see above for state d14 1 mode bits see above for state d13 odd parity ? includes all 16 bits odd parity ? includes all 16 bits d12 0 keep timer measurements see above for state 1 clear ?current measurement time? stored on the register of channel selected by d9:d7 see above for state d11 0 monitor mode selection bits see above for state d10 1 monitor mode selection bits see above for state d9 channel selected for current measurement see ta bl e 2 9 internal stored channel selections bits d8 d7 d6:d0 0 - current measurem ent of selected channel table 29. current measurement channel selections channel bit d9 bit d08 bit d07 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 functional description l9659 46/51 doc id 022048 rev 2 all other combinations for mosi bits d9:d7 will produce an error response of 0xd000. bits [d6:d0] current measurement data of selected squib channel. bit weight is nominally 25s for a total measurement time 3.175ms. monitor mode 3 monitor mode main information: status of fenx function - fenx pi n or?d with internal fenx latch status of current for each channel the spi message definition for mosi commands and miso responses in monitor mode 3 are defined below. 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 table 29. current measurement channel selections (continued) channel bit d9 bit d08 bit d07 msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mosi command for monitor mode 3 1 1 p 0 1 0 cfs 0 0 0 0 0 0 0 0 0 miso response for monitor mode 3 1 1 p 0 1 0 cfs por stat cf7 cf6 cf5 cf4 cf3 cf2 cf1 cf0 table 30. mosi monitor mode 3 bit definition bit mosi command miso response state description d15 1 mode bits see above for state d14 1 see above for state d13 - odd parity ? includes all 16 bits odd parity ? includes all 16 bits d12 0 - see above for state d11 1 - see above for state d10 0 - see above for state d09 status type 0 = current limit status 1 = fen function status 0 = current measurement status reported in bit d7:d0 1 = fen function status reported in d7:d0 d08 0 - por status d7:d0 0 - current measurement status of channels or fen status as indicated below l9659 functional description doc id 022048 rev 2 47/51 bit [d8] por status 0= reset occurred. bit cleared when read 1= normal with bit d9=0 cfs bit d7:d4 ?0000? bit d3: 0 = fen4 input or fen4 latch timer inactive 1 = fen4 input or fen4 latch timer active bit d2: 0 = fen3 input or fen3 latch timer inactive 1 = fen3 input or fen3 latch timer active bit d1: 0 = fen2 input or fen2 latch timer inactive 1 = fen2 input or fen2 latch timer active bit d0: 0 = fen1 input or fen1 latch timer inactive 1 = fen1 input or fen1 latch timer active note: the fen status is the result of the state of the fen input pin or?d with the fen latch timer. the fen latch timer will remain inactive until a transition of ?1? to ?0? on the fen input (assuming the pin was high for a minimum of 16 s). at that time the fen latch timer will be active and keep the internal fen signal active based on the programmed time (0ms, 128ms, 256ms or 512ms) for that particular fen function. with bit d9=1 cfs bit d7: 0 = current through channel 7 is below i meas 1 = current through channel 7 is above i meas bit d6: 0 = current through channel 6 is below i meas 1 = current through channel 6 is above i meas bit d5: 0 = current through channel 5 is below i meas 1 = current through channel 5 is above i meas bit d4: 0 = current through channel 4 is below i meas 1 = current through channel 4 is above i meas bit d3: 0 = current through channel 3 is below i meas 1 = current through channel 3 is above i meas bit d2: 0 = current through channel 2 is below i meas 1 = current through channel 2 is above i meas bit d1: 0 = current through channel 1 is below i meas 1 = current through channel 1 is above i meas bit d0: 0 = current through channel 0 is below i meas 1 = current through channel 0 is above i meas note: current status for ch annel is captured on the falling edge of chip select functional description l9659 48/51 doc id 022048 rev 2 monitor mode 4 monitor mode main information: revision l9659 id the spi message definition for mosi commands and miso responses in monitor mode 4 are defined below . the mosi response for the fi rst pass l9659 will be 0xed08 msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mosi command for monitor mode 4 1 1 p 0 1 1 0 0 0 0 0 0 0 0 0 0 miso response for monitor mode 4 1 1 p 0 1 1 id3 id2 id1 id0 r5 r4 r3 r2 r1 r0 table 31. mosi monitor mode 4 bit definition bit mosi command miso response state description d15 1 mode bits see above for state d14 1 see above for state d13 odd parity ? includes all 16 bits odd parity ? includes all 16 bits d12 0 - see above for state d11 1 mode selection see above for state d10 1 mode selection see above for state d9-d6 0 - ?0100? is device l9659 d5:d0 0 - revision information l9659 package information doc id 022048 rev 2 49/51 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 10. lqfp64 mechanical data and package dimensions. ' ! 0 ' 0 3 / 5 4 , ) . % ! . $ - % # ( ! . ) # ! , $ ! 4 ! ! ! ! " # % $ % % $ $ e + " 4 1 & 0 , , 3 e a t i n g 0 l a n e m m $ ) - m m i n c h - ) . 4 9 0 - ! 8 - ) . 4 9 0 - ! 8 ! ! ! " # $ $ $ e % % % , , + ? p l q ? p l q ? p d [ c c c , 1 & 0 x x m m & c c c revision history l9659 50/51 doc id 022048 rev 2 5 revision history table 32. document revision history date revision changes 26-jul-2011 1 initial release. 19-sep-2013 2 updated disclaimer. l9659 doc id 022048 rev 2 51/51 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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